Floating-gate based PN blending optoelectronic synaptic transistor for neural machine translation

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation...

PN-surfaces for blending applications

General theory of PN-surfaces (surfaces with rational offsets) is developed using dual Laguerre geometry and a universal rational parametrization of the Blaschke cylinder. This approach allows to construct new PN-blendings between two natural quadrics in many positions, and demostrate improved shape and lower parametrization degree than earlier proposed canal surface solutions. The construction...

C Hapter 3 Quasi Floating - Gate Mos Transistor

Byte-based Neural Machine Translation

This paper presents experiments comparing character-based and byte-based neural machine translation systems. The main motivation of the byte-based neural machine translation system is to build multilingual neural machine translation systems that can share the same vocabulary. We compare the performance of both systems in several language pairs and we see that the performance in test is similar ...

Chunk-based Decoder for Neural Machine Translation

Chunks (or phrases) once played a pivotal role in machine translation. By using a chunk rather than a word as the basic translation unit, local (intrachunk) and global (inter-chunk) word orders and dependencies can be easily modeled. The chunk structure, despite its importance, has not been considered in the decoders used for neural machine translation (NMT). In this paper, we propose chunk-bas...